Explore real samples, processing steps, result verification and process selection.
iMech Pro application images illustrate chip backside thinning, with a process path combining height measurement, leveling, visual positioning and suitable remaining-silicon-thickness metrology.
Read moreOverall and magnified flexible-board images illustrate observation of connections and fine traces after surface-material removal.
Read moreAssess component exposure, organic-coating changes and electrical condition separately, then qualify a staged MIP removal window through DOE.
Read moreLocal motherboard images illustrate Encap adhesive and PCB solder-mask removal, with inspection requirements for exposed regions, neighboring components and metal surfaces.
Read moreThe source records approximately 4 hours for an A13-marked sample and approximately 3 hours for another package, both using plasma only without laser preprocessing.
Read moreCombine small-area opening with peelable protective material to limit the processing region and support review of the target chip and neighboring structures.
Read moreExplore the challenges of stacked-die and memory-package decapsulation, two real application examples, and a combined iMech Pro and MIP route for subsequent die delayering.
Read moreA 3D package decapsulation case for semiconductor failure analysis: MIP plasma underfill removal after customer grinding, μbump inspection, and a proposed local workflow combining iMech Pro with iPlasma MIP.
Read moreCompare broad manual grinding with iMech Pro local opening for a published flip-chip micro-short case. Targeted access and MIP residue removal can help retain electrical connections for post-decapsulation retesting.
Read moreTell us about the package, your analysis objective and the structures to preserve. Together, we can define a suitable decapsulation process.
